1. Field of the Invention
Embodiments of the present invention generally relate to wafer probe cards for testing semiconductor devices and, more specifically, to enhancing the performance of wafer probe cards.
2. Description of the Related Art
Testing is an important step in the production of semiconductor devices for use. Typically, partially or fully completed semiconductor devices may be tested by bringing terminals disposed on an upper surface of a device to be tested—also referred to as a device under test (or DUT)—into contact with resilient contact elements, for example, as contained in a probe card assembly, as part of a test system. A test system controller may be coupled to the probe card assembly to send and receive test signals to and from the DUTs over a set of test channels. A test system controller with increased test channels can be a significant cost factor for a test system. Test system controllers have evolved to increase the number of channels and hence the number of devices that can be tested in parallel (sometimes referred to as multi-site testing). Unfortunately, the number of DUTs per wafer has typically outpaced the development of test system controllers. Conventionally, available channels are typically inadequate for testing all DUTs on a wafer at the same time.
Some test systems may have common test signals per site in a multi-site test configuration. Common test signals (sometimes referred to as global test signals) are test signals that can be applied to a plurality of DUTs being tested in a single touchdown. One technique to accommodate testing of components on a wafer with a limited number of test channels is to fan out a signal from a test system controller in the probe card assembly to multiple transmission lines. That is, a test signal normally provided to a single DUT can be fanned out to multiple DUTs in the probe card assembly. This technique can enable testing of an increased number of DUTs contemporaneously during a single touchdown for a fixed number of test system channels.
As the number of DUTs tested in a single touchdown increases, fanning out global signals from the test system controller becomes difficult to implement, if not impractical. The more DUTs that are tested simultaneously, the more fan out lines required on the probe card assembly. Including several thousands of lines on a probe card assembly is undesirable in terms of the required area and complexity of the components of the probe card assembly and in terms of cost.
Accordingly, there exists a need in the art for a method and apparatus for testing semiconductor devices that attempts to overcome at least some of the aforementioned deficiencies.